1. Field of the Invention
This invention relates in general to a processor processing method and a processor system. More specifically, the invention relates to a processor system having a digital signal processor (DSP) and a central processing unit (CPU), and a processing method suitable for the processor system.
2. Description of Related Art
Conventionally, regarding the signal processing for data processing etc, a general-purpose CPU or a ASIC (Application specific IC) dedicated to a particular useis used. The ASIC is designed so that its performance can be increased beyond that of the general-purpose CPU in the speed or in the cost aspect.
In addition, as the integration type IC becomes more popular, it begins to use products that are more widely used than the ASIC, for example the digital signal processor, such as a music chip or an image processing chip. Basically, the DSP is composed of a signal processing unit (processor unit) and a program storage unit to make the processor unit operate, which is installed as “middleware” having both characteristics of the hardware and the software.
Now, a system encircling a DSP is described. FIG. 56 is a diagram for explaining the configuration of a DSP system. A host CPU (CPU) 10 performs required settings, such as a boot process, on an upstream process unit and a downstream process unit. Additionally, downloading of the program is executed at the DSP 30. The upstream process unit 11 receives the settings from the CPU, and performs required operations to output signals to the DSP 30 when there is a requested process.
In general, the upstream process unit and the downstream process unit are respectively processing units for processing system external signals. In particular, the structure and the processing content are not limited. The programs are downloaded to the DSP 30 by the CPU 10, and the DSP 30 receives signals from the upstream process unit 11 and performs the signal processing according to the downloaded programs. Then, the processed signals are output to the downstream process unit 12.
FIG. 57 is an exemplary structure of the CPU 10 and the DSP 30. The CPU 10 has a read only memory (ROM) for storing a control program inside the CPU 10. The ROM stores the program downloaded to the DSP 30. The CPU 10 performs the download to the DSP in the boot process when the power is turned on or after the reset command.
FIG. 58 is a flow chart for describing the setting process of the CPU 10. The CPU 10 transmits the contents of a DSP program storage area in the ROM inside the CPU 10 to a memory unit in the DSP 30 according to the sequence shown in the drawing. As shown in FIG. 57, the DSP 30 consists of a processor unit 40 for performing the signal input, the signal process, and the signal output, and a memory unit 50 for storing the program that determines the processor's operations. Then, the DSP 30 performs processes according to the program downloaded to the memory unit 50.
FIG. 59 is a chart for showing the sequence that the system in FIG. 56 actually operates. First, when starting the power, a start request is acknowledged to the CPU 10 from external. As the CPU 10 receives the start request, the CPU 10 performs the boot processes to the upstream process unit 11 and the downstream process unit 12, and then sets each component. The drawing only shows the settings of the DSP 30. The process settings from the CPU 10 mean that the programs are downloaded to the DSP 10.
After the program is downloaded, the DSP 30 goes into a standby status for input signal, and returns a response of setting complete to the CPU. The CPU 10 acknowledges that the upstream process unit 11 is ready for starting the process. The upstream process unit 11 transmits signals to the DSP 30 at any time, the DSP 30 then processes the received signals and outputs to the downstream process unit 12.
As described above, by using the DSP, the hardware portion has a more generalized structure, and when using a variety of different hardware programs, the subroutine reuse probability is high and therefore the processing range can be widened.
However, the conventional technology has the following problems. Recently, the operation speed of the IC has increased greatly, and the design burden is increased for each product because the product cycle time is reduced. The specification may have to be versioned up when designing the ASIC or ordering the ASIC, and a portion of the specification may have to be changed. Therefore, it is difficult to properly keep up with the technology revolution. Additionally, for the ASIC chip, because the process content or the parameters required for the process are fixed, application is limited. Furthermore, using the conventional DSP cannot widen the application range.